One of the most anticipated releases for late 2008 is Intel's Nehalem processor that was recently named Intel Core i7. Looking forward, according to internal slides, Intel plans to release a 32nm shrink of Nehalem, codenamed Westmere at the end of 2009.
The next new architecture after Nehalem is codenamed Sandy Bridge (formerly known as Gester) and will be built on a 32nm process. While details are scarce, Intel is hard at wesl on its development and details have begun to trickle out. Sandy Bridge will features some key improvements. It will support wider vectors which Intel says allows far more power efficient floating point operations. It also will feature "advanced data rearrangement" involving the use of 256 bit primitives. Intel says this will improve cache coordination and help to speed the flow of data. The new architecture will support three and four operand instructions and non destructive syntax to minimize register copies and allow for extensibility. The architecture also feature "flexible unaligned memory access support" which Intel indicates will allow computations to be immediately performed on data loaded from memory. Intel also will offer up an extensible new opcode (VEX) which it says will reduce code size. The overall result of the improvements will be as much as 90% in certain mathematically intensive operations such as matrix multiplies according to Intel.
With the Sandy Bridge processors expected to land in 2010, 2011 will bring a shrink codenamed Ivy Bridge which will be madd at the 22nm node.
Finally the next new Haswell architecture will arrive. It's still in an early stages but Intel has big plans for it. Early reports indicate that it will have 8 physical cores by default and revolutionary power saving features.
Intel was rather tight-lipped about architectural details on its upcoming GPU, Larrabee. Also detailed in brief was the possible Atom succesor, the upcoming Tolapai processor formerly codenamed Pineview. Tolapai is a System On a Chip (SOC) in that it will feature an integrated DDR2 memory controller, an integrated graphics core, and a full chipset which features PCI, ethernet, serial, and peripheral connections. The chips processor will be an x86 design based on the Pentium M and will consist of 148 million transistor. It will come in a 37,5 mm X 37,5 mm package. It will launch with 600 MHz or 1200 MHz clocked models. The new integrated system is expected to be usee in Netbooks as well as other divese applications and will compete with ARM Holdings' SOC offerings.
Wednesday, August 20, 2008
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